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hm530281r series 331,776-word 8-bit frame memory ade-203-251b rev. 1.0 june 6, 1997 description the hm530281r series memory products provide completely asynchronous i/o and operate at the high speed of 50 mhz. the hm530281r series memory products provide reset, jump, and line increment/hold pointer control functions that can be used in synchronization with independent clocks on each of the i/o ports. memory can be accessed immediately without any waiting period after the execution of these functions. in addition to the fifo function, the 281r series products support an address structure that is compatible with hdtv, ntsc, and pal standards, and can be used in a wide range of applications, such as noise reducers, tbc (time-based correction), inter-frame yc separation, and special function modes (e.g., multi-freeze, p-in-p) in the digital tv, vcr, and video camera application. they are also appropriate for use as inter-system speed conversion buffer memories in communications systems, as cache memories of hdd and mod, and as frame buffer of vga. features organization: 331,776-word 8-bit completely asynchronous operation of the serial read port and write port. ? internal generation of read and write addresses ? internal memory operation control provided on-chip high speed read/write cycle time: 50 mhz reset, jump functions ? independent execution for read and write ports ? can be executed with arbitrary timing ? allow immediate access after execution (read/write) (for the jump function, when the address setup is complete) ? jump address specifiable in 32-word units 2 dimensional address line increment/hold address pointer control function window scan function
datasheet title 2 can handle hdtv, ntsc, and pal standards ? line length: up to 1152 bits (arbitrary line lengths can also be handled by using the line reset function.) ? line count: up to 324 lines built-in self-refresh eliminates the need for external refresh control. power supply voltage: v cc = 5.0 v 10%. ordering information type no. cycle time memory organization package hm530281rtt-20 HM530281RTT-25 hm530281rtt-34 hm530281rtt-45 20 ns 25 ns 34 ns 45 ns 331,776 words 8 bits *2 1152 dots 288 lines 8 bits *3 1024 dots 324 lines 8 bits 44-pin tsop (ttp-44db) notes: 1. selectable following two kinds of addressing mode by mode pins 2. 1 dimensional addressing mode 3. 2 dimensional addressing mode pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 dout0 dout1 dout2 dout3 dout4 dout5 dout6 dout7 v v oe cgr rck rrs rlrs rclr rwnd ras rad test1 test2 test3 din0 din1 din2 din3 din4 din5 din6 din7 v v we cgw wck wrs wlrs wclr wwnd was wad mode0 mode1 test0 ss (top view) cc ss cc
datasheet title 3 pin description functions symbol 2 dimensional address 1 dimensional address din0 to din7 data input data input dout0 to dout7 data output data output wck write clock write clock rck read clock read clock wrs write reset write reset rrs read reset read reset we write enable write enable oe output enable output enable cgw write clock gate write clock gate cgr read clock gate read clock gate was write address set write address set wad write address write address ras read address set read address set rad read address read address wlrs write line reset v cc or gnd rlrs read line reset v cc or gnd wwnd write window mode v cc or gnd rwnd read window mode v cc or gnd wclr write clear v cc or gnd rclr read clear v cc or gnd mode 0 to 1 mode selection input mode selection input v cc power supply power supply v ss ground ground test0 to test3 connect to ground connect to ground
datasheet title 4 block diagram dout oe write data register memory array 1152 dot 288 line 8 1024 dot 324 line 8 10368 dot 32 word 8 * * * memory controller write counter read counter din we refresh counter wck cgw wrs was wad wlrs wwnd wclr rck cgr rrs ras rad rlrs rwnd rclr 32-word 8 32-word 8 32-word 8 32-word 8 8 1 1 1 8 write data buffer read data buffer read data register note : 1. selected by the mode pin absolute maximum ratings parameter symbol value unit pin voltage *1 v t C1.0 to +7.0 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c storage temperature (when biased) tbias C10 to +85 c note: 1. the permissible values with respect to v ss .
datasheet title 5 recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit power supply voltage v cc 4.5 5 5.5 v v ss 000v input voltages v ih 2.7 6.5 v v il C0.5 *1 0.6 v note: 1. when the pulse width is under 10 ns, v il min = C3.0 v. dc characteristics (v cc = 5.0 v 10%, v ss = 0 v, ta = 0 to +70 c) hm530281-20 hm530281-25 hm530281-34 hm530281-45 test parameter symbol min typ max min typ max min typ max min typ max unit conditions operating power supply current i cca 110 135 90 120 70 95 55 75 ma iout = 0, t wcc = t rcc = min standby power supply current i ccs 15 25 15 25 15 25 15 25 ma v cc = 5.5 v wck, rck = l fix input leakage current i li C10 10 C10 10 C10 10 C10 10 ma v cc = 5.5 v, vin = v ss to v cc output leakage current i lo C10 10 C10 10 C10 10 C10 10 ma oe = vin vout = v ss to v cc output voltages v ol 0.4 0.4 0.4 0.4 v i ol = 2.1 ma v oh 2.4 2.4 2.4 2.4 v i oh = C1.0 ma capacitance *1 parameter symbol typ max units test conditions input capacitance cin 5 pf vin = 0 v output capacitance cout 7 pf vout = 0 v note: 1. these parameters are sampled values, not values measured for all units.
datasheet title 6 ac characteristics test conditions input pulse level: v ss to 3.0 v input rise/fall time: 3 ns i/o timing reference level: 1.5 v output load: 1 ttl + 50 pf (including jig and scope capacitances) hm530281r-20 hm530281r-25 hm530281r-34 hm530281r-45 parameter symbol min max min max min max min max unit write clock cycle time t wcc 20 25 34 45 ns write clock pulse width (high) t wc 8 10 12 15 ns write clock pulse width (low) t wcp 8 10 12 15 ns wrs setup time t wrs 7 8 10 10 ns wrs hold time t wrh 7 8 10 10 ns data input setup time t ds 5 555ns data input hold time t dh 6 666ns cgw setup time t wgs 7 8 10 10 ns cgw hold time t wgh 7 8 10 10 ns we setup time t wes 5 555ns we hold time t weh 6 666ns read clock cycle time t rcc 20 25 34 45 ns read clock pulse width (high) t rc 8 10 12 15 ns read clock pulse width (low) t rcp 8 10 12 15 ns rrs setup time t rrs 7 8 10 10 ns rrs hold time t rrh 7 8 10 10 ns access time from rck t rac 18 23 25 30 ns output hold time t oh 6 666ns output enable time t olz 0 000ns output enable access time t oac 18 20 25 25 ns output disable time t ohz 0 15 0 18 0 20 0 20 ns cgr setup time t rgs 7 8 10 10 ns cgr hold time t rgh 7 8 10 10 ns was setup time t wss 7 8 10 10 ns was hold time t wsh 7 8 10 10 ns
datasheet title 7 ac characteristics (cont) hm530281r-20 hm530281r-25 hm530281r-34 hm530281r-45 parameter symbol min max min max min max min max unit ras setup time t rss 7 8 10 10 ns ras hold time t rsh 7 8 10 10 ns write address input setup time t was 5 555ns write address input hold time t wah 6 666ns re ad ad dr es s i nput set up ti me t ras 5 555ns read address input hold time t rah 6 666ns wlrs setup time t wls 7 8 10 10 ns wlrs hold time t wlh 7 8 10 10 ns rlrs setup time t rls 7 8 10 10 ns rlrs hold time t rlh 7 8 10 10 ns wclr setup time t wcls 7 8 10 10 ns wclr hold time t wclh 7 8 10 10 ns rclr setup time t rcls 7 8 10 10 ns rclr hold time t rclh 7 8 10 10 ns wwnd setup time t wwds 7 8 10 10 ns wwnd hold time t wwdh 7 8 10 10 ns rwnd setup time t rwds 7 8 10 10 ns rwnd hold time t rwdh 7 8 10 10 ns
datasheet title 8 input and output pin functions d in 0 to d in 7 (data input) input: the d in pins input 8 bits of data. data is input on the rising edge of the cycle of wck that follows a low level on both cgw and we . d out 0 to d out 7 (data output) output: the d out pins output 8 bits of data. data output is synchronized with the rck clock, and the access time is specified from the rising edge of the rck cycle. wck (write clock) input: wck is the write clock input pin. the input of write data is synchronized with this clock. write data is input on the rising edge of the cycle of wck that follows a low level on both cgw and we , and when cgw is low, the internal write address pointer is incremented at the same time. input of the write jump address is also synchronized with this clock. the 14 bits or 15 bits of the write jump address are read in sequentially from the wck cycle that set was low, irrespective of write data acquisition. rck (read clock) input: rck is the read clock input pin. read data is output in synchronization with this clock when both cgr and oe are low, and when cgr is low, the internal read address pointer is incremented at the same time. input of the read jump address is also synchronized with this clock. the read jump address is read in sequentially starting at the rck cycle in which ras was set low, independently of read data output. wrs (write address pointer reset) input: wrs is a reset signal input that resets the write address pointer to 0 when was and wlrs are high, resets to the head of the line currently being written when was is high and wlrs is low, and jumps to the preset write jump address when was is low. *1 only the falling edge of this reset input is detected, and, on the first wck cycle following that falling edge, a write cycle to the set address is started immediately. rrs (read address pointer reset) input: rrs is a reset signal input that resets the read address pointer to 0 when ras and rlrs are high, resets to the start of the line currently being read when ras is high and rlrs is low, and jumps to the read jump address when ras is low. *1 only the falling edge of this reset input is detected, and, on the first rck cycle following that falling edge, a read cycle at the set address is started immediately. we (write enable) input: we is an input signal that controls the enabling/disabling of the data input pins. when we is low, input data is acquired on the wck cycle, and when we is high, data input is disabled and the previous memory data is maintained. note that the write address pointer is incremented by the wck write clock without regard for the level of we . oe (output enable) input: oe is an input signal that enables/disables the data output pins. when oe is low, data output is enabled, and when high, data output is disabled and the output pins go to the high impedance state. note that the read address pointer is incremented by the rck read clock without regard for the level of oe . therefore, data can be jumped over during read simply by disabling output with oe . cgw (clock gate for write) input: cgw is an input signal that enables/disables incrementing of the internal write address pointer. when cgw is low, the write address pointer is incremented in synchronization with the wck write clock, and when high, incrementing is stopped. therefore time axis compression can be easily implemented without stopping the write clock by using cgw .
datasheet title 9 cgr (clock gate for read) input: c gr is an input signal that enables/disables incrementing of the internal read address pointer. when cgr is low, the read address pointer is incremented in synchronization with the rck read clock, and when high, incrementing is stopped. therefore time axis expansion can be easily implemented without stopping the read clock by using cgr . was (write address set and jump) input: was is an input signal that initiates write jump address input when wrs is high and jumps to the previously input write jump address when wrs is low. the falling edge of this input signal is detected, and either a write jump address input is initiated or a jump to the previously input write jump address is executed on the first wck cycle following the fall of was . wad (write jump address) input: wad is the input pin for the write jump address. the 14/15 bits of the write jump address are read in sequentially from the high order bit, starting at the wck cycle (when wrs was high) in which was was set low. *2 ras (read address set and jump) input: ras is an input signal that initiates read jump address input when rrs is high and jumps to the previously input read jump address when rrs is low. the falling edge of this input signal is detected, and either the read jump address input is initiated or the jump to the previously input read jump address is executed on the first wck cycle following the fall on ras . rad (read jump address) input: rad is the input pin for the read jump address. the 14/15 bits of the write jump address are read in sequentially from the high order bit, starting at the rck cycle (when r r s was high) in which r as was set low. *2
datasheet title 10 wlrs (write line reset) input (in 2 dimensional addressing mode): wlr s is an input pin for resetting the write address pointer to the start of the line from an arbitrary dot for each line. *3 only the falling edge of this signal is detected, and, on the first wck cycle following that falling edge, the write address pointer is set to the head of the next line when wrs is high, and to head of the current line when wrs is low. *3 rlrs (read line reset) input (in 2 dimensional addressing mode): r lr s is an input pin for resetting the read address pointer to the start of the line from an arbitrary dot for each line. *3 only the falling edge of this signal is detected, and, on the first rc k cycle following that falling edge, the write address pointer is set to the head of the next line when rrs is high, and to head of the current line when rrs is low. *3 wwnd (write window scan) input (in 2 dimensional addressing mode): wwnd is an input signal that specifies the use of the window scan function. when executing a write jump with wrs and was low, if wwnd is set low at the same time, a scan of the window region that takes that write jump address as its starting point will begin (see note below). rwnd (read window scan) input (in 2 dimensional addressing mode): rwnd is an input signal that specifies the use of the window scan function. when executing a read jump with rrs and ras low, if rwnd is set low at the same time, a scan of the window region that takes that read jump address as its starting point will begin. *4 wclr (write clear) input: wclr is an input signal that, independently of the levels on wrs , was , wlrs and wwnd resets the write address pointer to 0 and clears the window scan function. this function is executed immediately in the wck cycle in which wclr was set low. this clear operation should also be performed after applying power to the hm530281r. rclr (read clear) input: rclr is an input signal that, independently of the levels on rrs , ras , rlrs and rwnd resets the read address pointer to 0 and clears the window scan function. this function is executed immediately in the rck cycle in which rclr was set low. this clear operation should also be performed after applying power to the hm530281r. notes: 1. the reset destination in window scan mode changes as follows. reset to 0: reset to the window start. reset to line start: reset to the point at the left edge of the window for the line 2. addressing mode address structure input address 1 dim. add. (fifo) 0 to 10,367 blocks address bits a 13 to a 0 2 dim. add. (1) 32 horizontal blocks by 324 vertical lines line address bits v 8 to v 0 , horizontal address bits h 4 to h 0 2 dim. add. (2) 36 horizontal blocks by 288 vertical lines. line address bits v 8 to v 0 , horizontal address bits h 5 to h 0 3. when window scan mode is set, the reset is to the point at the left edge of the window for the line. 4. when window scan is set, the horizontal address of the pointer reset destination when increment/hold is executed will be the left edge of the window. also, when a reset is executed, the pointer will be reset to the starting point of the window. thus it is possible to scan arbitrary window regions within the screen independently for read and write by using these line reset and reset functions.
datasheet title 11 memory structure the memory is organized as 331,776-word of 8-bit each, and these words can be accessed sequentially, since the address pointer can be incremented by inputting a clock signal. addresses are allocated corresponding to 32 word blocks. the mode pins switch between the three addressing modes shown below. mode 0 mode 1 addressing mode address structure capacity 0 0 1 dim. add. (fifo) 0 to 10,367 blocks 331,776 words 1 0 2 dim. add. (1) 32 horizontal blocks by 324 vertical lines 1024 dots by 324 lines 0 1 2 dim. add. (2) 36 horizontal blocks by 288 vertical lines 1152 dots by 288 lines notes: 1. in 1 dimensional addressing mode, blocks 0 to 10367 are accessed cyclically. 2. in the 2 dimensional addressing modes, the line head can be reset at an arbitrary dot on each line. operations write write operation: when the we and cgw inputs are low, 8 bits of write data are input in synchronization with the wck clock. the input data is read in to the word indicated by the address pointer on the next rising edge of the wck cycle. this allows read data and write data to be handled with the same clock, and cascade connections to be easily implemented. write reset operations: when cgw is low, by setting wrs low, the write address pointer can be set immediately on that wck cycle to the address 0 block head. this operation can be executed independently of the input level of we . (see notes on usage 15 on the operation when cgw is high.) write address pointer increment operations: the write address pointer is incremented in synchronization with wck when cgw is low. it is possible to apply a write mask in wck clock units by setting the we input high. in this case, the previous memory data will be retained. the write address pointer increment function can be stopped by setting the cgw input high. this allows time axis compression to be implemented easily. (see notes on usage 7, 9 and 10 for interval specifications of write system reset operations. *1 ) note: 1. the write system reset operation stands for write reset, write jump, write window reset, write line reset and write clear.
datasheet title 12 we and cgw input level, write address pointer, and data input state relationship wck rising edge cgw we internal write address pointer data input l l incremented enable l h disable (memory data is retained) h stopped note: data is input when the we input is low. read read operation: 8 bits of read data are output in synchronization with the rck clock when the oe and cgr inputs are low. the access time is stipulated from the rising edge of the rck clock. read reset operations: when cgr is low, by setting rrs low, the read address pointer can be set immediately on that rck cycle to address 0 and the data will then be output. this operation can be performed independently of the input level of oe . (see notes on usage 14 on the operation when cgr is high.) read address pointer increment operations: the read address pointer is incremented in synchronization with rck when cgr is low. data outputs go to the high impedance state when the oe input is set high. the reset address pointer increment function can be stopped by setting the cgr input high. this allows time axis expansion to be implemented easily. (see notes on usage 7, 8 and 10 for interval specifications of read system reset operations. *2 ) note: 2. the read system reset operations stands for read reset, read jump, read window reset, read line reset and read clear. relation between the oe and cgr input levels and the read address pointer and data output states rck rising edge cgr oe internal read address pointer data output l l incremented output l h high impedance h l stopped output data held h h high impedance note: data is input when the oe input is low. line reset (write line reset and read line reset, in 2 dimensional addressing modes) when the 281r series products are used in 2 dimensional addressing modes, the line length can be set to be either 1024 dots (2 dimensional (1)) or 1152 dots (2 dimensional (2)). in these modes, after accessing the
datasheet title 13 data at the last dot (address) on each line, address pointer incrementing is stopped. access is restarted at either the first dot at the head of the next line or at the first dot at the head of the current line by executing either a line increment or a line hold, respectively. also, since these line reset operations can be executed at any arbitrary point in the middle of a line, an arbitrary line length (of between 64 dots and the actual line length) can be realized. line increment operation: in case clock gate signal ( cgw , cgr ) is low, the read and write line increment operations are executed by setting rlrs low and rrs high, and setting wlrs low and wrs high respectively. when these operations are executed, the next access goes immediately to the starting dot of the next line. line hold operation: in case clock gate signal ( cgw , cgr ) is low, the read and write line hold operations are executed by setting rlrs and rrs low, and setting wlrs and wrs low respectively. when these operations are executed, the next access goes immediately to the starting dot of the current line. note that the read line hold operation is invalid on the first line following a 0 reset or jump. in this case, the same effect can be achieved by re-executing the reset or jump operation (resetting only the h address to 0). if the reset interval specifications are met (see notes on usage 1 to 3), the line reset operation can be performed on an arbitrary rck/wck clock cycle without regard for the levels of the oe and we inputs. (see notes on usage 15 and 16 on the operation when clock gate signal ( cgw , cgr ) is high.) jump (independent functions for read and write) it is possible to set the address pointer to the start address of an arbitrary block in 32 word units. after initializing a jump address setup for read and/or write, after 64 wck or 64 rck cycles, it is possible to execute a jump to that address (random access in 32 word by 8 bit units) independently for read and write. (see notes on usage 12 on the jump operation to 0 address and line end address.) jump address setup: the read and write jump addresses are serially input independently from the rad and wad pins in synchronization with the rck and wck clock inputs respectively. address input start is enabled by setting the ras and/or was inputs low for read and write respectively, and 14/15 bits of jump address are input sequentially starting with that cycle. *10 note that the read and write operations can continue independently of this address input operation. jump address setup is executed regardless of we , cgw and oe , cgr . following the start of address input, it is possible to mask the input of address bits below an arbitrary bit position by returning ras or was to the high level at the desired bit position. this can be convenient in applications that need to jump a fixed interval, since the low order bits of the address will be fixed. when all 14 bits of an address are to be input, be sure to hold ras and was low for the full 14-clock period. jump operation: in case clock gate signal ( cgw , cgr ) is l, the jump operation is executed by setting rrs and ras low for read, and by setting wrs and was low for write, and the address set is accessed immediately from that rck or wck cycle. note that as long as the interval specifications listed in notes 7 to 9 are met, the jump operation can be executed on any rck or wck cycle without regard for the values of oe and we . (see notes on usage 14 and 15 on the operation, when clock gate signal ( cgw , cgr ) is high.)
datasheet title 14 window scan (independent functions for read and write) the window scan function can be used with either the 2 dimensional (1) or (2) addressing modes, and is a function which scans a rectangular region with an arbitrary starting point. the jump address setup function (see jump address setup above) is used to specify the starting point initiating window scan: the window scan function is started by setting wwnd to low for read or rwnd low for write, and executing a read or write jump operation (see jump operation above). window scan will start immediately from that cycle. window scan operation: when the window scan function is started, one of the functions described below will be executed independently for read and write. *11 also note that as long as the interval conditions listed in notes 7 to 9 are met, these operations can be executed at arbitrary dots without regard for the address block organization. clearing window scan: the window scan function is turned off either by executing a reset or jump with r wnd (for read) or wwnd (for write) set high, or by executing the clear operation described in section clear below. note that both setting and clearing window scan mode are executed independently of oe and we . (see notes on usage 14 and 15 on the operation when clock gate signal ( cgw , cgr ) is high.) operation address pointer control reset reset to the first dot at the start of the window. line increment reset to the first dot at the left edge of the window on the next line. line hold reset to the first dot at the left edge of the window on the current line.
datasheet title 15 overview of the window scan operation: 0 0 31 1 63 2 1023(1151) 31(35) horizontal (dot) horizontal address (h) first point of the screen first point of the window window area (v, n) (v + 1, n) (v, n + n) (m + m, n + n) reset line hold vertical (line) 323 (287) 0 note: 1. line increment (m, n) m and n are addresses, m is in line units, n is units of 32 dots, and m and n are in line and dot units respectively. clear (independent functions for read and write) the clear function both resets the address pointer to 0 without regard for the value on wrs , was , wlrs , wwnd , rrs , ras , rlrs and rwnd , and if window mode is set, clears window mode. clear operation: when clock gate signal ( cgw , cgr ) is low, the clear operation can be executed on any cycle by setting the rclr pin low for read and the wclr pin low for write. when the interval conditions listed in notes on usage 7 to 10 are met, clear operation is executed at any time without regard of the level on we and oe . (see notes on usage 14 and 15 on the operation when clock gate signal ( cgw , cgr ) is high) access of new and previous data new data access (follow-up read out of data currently being written): written data can be read out 160 wck cycles after it is written. however, it is necessary to execute the read jump address setup operation outside the time period between 32 wck cycles before write to that address is started and 32 wck cycles after write to that address is completed.
datasheet title 16 it is possible to read out the new data of 32 word block when jumping to an address at least 128 wck clock cycles after write to that address was started. note that in this case, there is more than enough time for the read jump address setup operation even if it is begun 32 or more clock cycles after the completion of the write operation. it is possible to read out the new data of less than 32 word block when 128 wck clock after write system reset was input. starting and clearing window scan: window off window on (reset) (line increment) (line hold) (jump) (reset to the window origin point) (line increment) (line hold) clear (reset) (jump) (clear) start (window jump) new setup (window jump) (address setup) at least 96 wck clock are necessary between completion 32 word block data input and starting previous address of 32 word block data output. generally this mean, 160 wck clock separation between write and read address pointer. previous data access (reading out data prior to that of the current write operation): the previous data can be read out up to 32 wck clock cycles after the write operation. therefore, these memories can be used to provide delay times of between 160 and 331,808 (331,776 + 32) clock cycles.
datasheet title 17 power on wait at least 100 m s after power-on to begin operation. at this time the write and read address pointers are undefined. the following operation should be executed. cgw and cgr should be hold low. reset cycle when 1 dimensional addressing mode. clear cycle when 2 dimensional addressing mode. dummy cycle of over 64 wck and 64 rck clock cycle. then, initiate the desired operating mode by providing the signal input combination given by the truth tables below. function table note: description of operations of function table is based on the operation on condition cgw , we and cgr , oe is low. 1 dimensional addressing modes write wck rising edge wrs was operation h h normal state in the normal state, the write address pointer is incremented in synchronization with wck. l h reset the write address pointer is reset to 0. l l jump jump to the address a to which the write address pointer is set. h l address setup the write jump address is input. read rck rising edge rrs ras operation h h normal state in the normal state, the read address pointer is incremented in synchronization with rck. l h reset the read address pointer is reset to 0. l l jump jump to the address a to which the read address pointer is set. h l address setup the read jump address is input.
datasheet title 18 2 dimensional addressing modes (when window scan is not used) write *1 operation levels at the rise of wck write address pointer write jump wrs was wlrs wwnd wclr control address notes h h h h h normal state incremented in synchronization with wck 2 l h h h h reset reset to (0, 0) l l h h h jump jump to the set address a h l h h h address set set h h l h h line increment reset to the first bit of the next line 2 l h l h h line hold reset to the first bit of the current line 2 ??? ? l clear reset to (0, 0) note: (: v ih or v il ) read *1 operation levels at the rise of wck read address pointer read jump rrs ras rlrs rwnd rclr control address notes h h h h h normal state incremented in synchronization with rck 3 l h h h h reset reset to (0, 0) l l h h h jump jump to the set address a h l h h h address set set h h l h h line increment reset to the first bit of the next line 3 l h l h h line hold reset to the first bit of the current line 3 ??? ? l clear reset to (0, 0) note: (: v ih or v il )
datasheet title 19 2 dimensional address modes (when window scan is not used) write operation levels at the rise of wck write address pointer control write jump window mode after wrs was wlrs wwnd wclr window mode off window mode on address execution notes l h h h h reset reset to (0, 0) off h h h h normal state incremented in synchronization with wck 4 h h l h line increment to the first bit of the next line to the left edge of the window on the next line l h l h line hold to the first bit of the current line to the left edge of the window on the current line h l h h address set set l l h h h jump jump to the set address a off l l h l h window jump jump to the set address a on 6 l h h l h reset reset to the window origin point a l clear reset to (0, 0) off note: (: v ih or v il )
datasheet title 20 read operation levels at the rise of wck read address pointer control rrs ras rlrs rwnd rclr window mode off window mode on read jump address window mode after execution notes l h h h h reset reset to (0, 0) off h h h h normal state incremented in synchronization with rck 5 h h l h line increment to the first bit of the next line to the left edge of the window on the next line l h l h line hold to the first bit of the current line to the left edge of the window on the current line h l h h address set set l l h h h jump jump to the set address a off l l h l h window jump jump to the set address a on 6 l h h l h reset reset to the window origin point a l clear reset to (0, 0) off (: v ih or v il ) notes on usage. 1. hold the wwnd and rwnd pin high when window mode is not used. 2. the write address pointer is incremented up to the last dot on the current line, and then stopped. writing is started immediately from the first dot on the next line by execution of the line increment operation. also, writing is started immediately from the first dot on the current line by execution of the line hold operation. 3. the read address pointer is incremented up to the last dot on the current line, and then stopped. reading is started immediately from the first dot on the next line by execution of the line increment operation. also, reading is started immediately from the first dot on the current line by execution of the line hold operation. 4. the write address pointer is incremented up to the last address on the line, and then stopped. writing is started immediately from the first dot on the next line or the left edge of the window by execution of the line increment operation.
datasheet title 21 5. the read address pointer is incremented up to the last address on the line, and then stopped. reading is started immediately from the first dot on the next line or the left edge of the window by execution of the line increment operation. 6. it is possible to move directly from an old window to a new window in window mode by setting up a new jump address and executing a window setup jump operation. however, the new jump address should be input after access to the last line of the old window. 7. read system reset operations (read reset, read jump, read window reset, read line reset and read clear) and the read address set up operation cannot be executed for consecutive rck clock cycles. similarly write system reset operations (write reset, write jump, write window reset, write line reset and write clear) and the write jump address setup operation cannot be executed for consecutive wck clock cycles. 8. read system reset (read reset, read jump, read window reset, read line reset and read clear) operations and read jump address set operations must be performed at times separated by at least 64 rck clock cycles. (there is no need to use only 32 word addressing units, and these operations can be performed on any clock cycle). 9. write system reset operations (write reset, write jump, write window reset, write line reset and write clear) must be performed at times separated by at least 64 wck clock cycles. when address is input, write/read system reset can not be executed. 10. it is possible to input the write system reset in the middle of 32 word unit addressing. in this case, not only must the condition of note 8 be met, but furthermore, pairs of write system resets for units of less than 32 words must be separated by at least 160 wck clock cycles. when the write system reset is executed at less than 32 words, the data up to the point to which the address pointer has advanced will be written, and the remaining data will retain the old values. (note that after the completion of a write of less than 32 words, a write reset is required to write the data for the last address into the memory array.) 11. addressing mode address structure input address 1 dim. add. (fifo) 0 to 10,367 blocks address bit a13 to a0 2 dim. add. (1) 32 horizontal blocks by 324 vertical lines line address bits v8 to v0, horizontal address bits h4 to h0 2 dim. add. (2) 36 horizontal blocks by 288 vertical lines line address bits v8 to v0, horizontal address bits h5 to h0 12. specifiable window sizes horizontal: between 64 dots and the length of the line. vertical: between 1 line and the maximum number of lines. 13. location 0 and line end cannot be specified as a jump address. use a reset to access location 0 . 14. any number of read system reset operations can be input when cgr is high but in this case the only first reset is effective. this read system reset operation (read reset, read jump, read window reset, read line reset and read clear) is executed at the rising edge of the rck just after cgr is set low. 15. any number of write system resets can be input when cgw is high, but the only first reset is effective. this write system reset operation is executed at the rising edge of the wck just after cgw is set to low. 16. when window scan mode is used any case after power on, wwnd and wrs or rwnd and rrs pins are should be input same signal.
datasheet title 22 supplement if the read system reset interval (at least 64 rck clock cycles) of note 7, or the write system reset interval for less than 32 word units (and at least 160 wck clock cycles) are not provided (see note 9), it is possible for the 32 words of data of the first address after the reset to be invalid, or for the first write of less than 32 words following the write reset to fail to occur. however, even in this case, address pointer control will function correctly, and valid data will be output for the second and following addresses. (however, in this case the condition of note 8 and the 32 clock or longer read system reset/read jump address interval must be provided.) timing waveforms write cycle write address reset t wrs t ds t dh d(n - 2) d(n - 1) d(n) d(0) d(1) d(2) add 'x' add '0' high wck wrs was din t wrs t wrt t wc t wcc t wcp cycle n - 1 cycle n cycle 0 cycle 1 cycle 2 note: the write address pointer is reset to 0 starting with the wrs low cycle. only the falling edge of the wrs signal is detected. adequate margin is provided if the rise occurs at least one clock cycle before the next fall.
datasheet title 23 write clock gate cycle n - 1 cycle n clock gate cycle cycle n + 1 cycle n + 2 d(n - 2) d(n) d(n + 1) high wck wrs was din note: t wcc d(n + 2) d(n - 1) cgw we t wgs t wgh high low during cycles where cgw is high, the write address pointer is not incremented, and the d data is not written. in write enable cycle n - 1 cycle n cycle n + 2 cycle n + 3 d(n - 2) d(n) d(n + 2) high d(n + 3) d(n - 1) high low t wcc t weh t wes t weh t wes note: wck wrs was din cgw we although the write address pointer is incremented on a cycle where we is high, the d data is not written, and the previous memory data is retained. in
datasheet title 24 read cycle read address reset cycle n - 1 cycle n cycle 0 cycle 1 cycle 2 rck rrs ras dout note: d(n - 2) d(n - 1) d(n) d(0) d(1) d(2) t rcc t rc t rrh t rac t oh t rcp t rrs add'x' add'0' high t rrs the read address pointer is reset to 0 from the cycle where rrs was low. only the falling edge of the rrs signal is detected. adequate margin is provided if the rise occurs at least one clock cycle before the next fall. read clock gate rck rrs ras dout d(n - 2) d(n - 1) t rcc cycle n - 1 cycle n clock gate cycle cycle n + 1 cycle n + 2 cgr oe t oh t rgh t rgs t rac d(n) d(n + 1) d(n + 2) high high low note: during cycles where cgr is high, the read address pointer is not incremented, and the output data is retained.
datasheet title 25 output enable cycle n - 1 cycle n disable cycle (n + 1) cycle n + 2 cycle n + 3 t rcc t rac t ohz t olz t oac rck rrs ras dout cgr oe high high low note: high-z d(n - 2) d(n - 1) d(n) d(n + 2) d(n + 3) during cycles where oe is high, the output goes to the high impedance state, and the read address pointer is incremented. line reset write line increment d(n - 1) d(n) d(0) d(1) d(2) t wcc t wlh t wls t ds t dh add(v, h) add(v + 1.0) high high high wck wlrs wrs din wwnd wclr note: n - 1 n 0 1 2 t wls the line address v is incremented, and the horizontal address h is reset to 0.
datasheet title 26 read line increment t rcc add (v, h) high high high rck rlrs rrs dout rwnd rclr note: n - 1 n 0 1 2 d(n - 1) d(n) d(0) d(1) d(2) t rlh t rls t oh t rac add (v + 1,0) t rls the line address v is incremented, and the horizontal address h is reset to 0. write line hold d(n - 1) d(n) d(0) d(1) d(2) t wcc t wls t ds t dh add(v, h) add(v, 0) high high high wck wlrs wrs din wwnd wclr note: n - 1 n 0 1 2 t wrs t wlh t wrh t wls t wrs the line address v is held as it is, and the horizontal address h is reset to 0.
datasheet title 27 read line hold t rcc t rls add(v, h) add(v, 0) high high high rck rlrs rrs dout rwnd rclr note: n - 1 n 0 1 2 t rrs t rrh d(n - 1) d(n) d(0) d(1) d(2) t rdh t rlh t rac t rls t rrs the line address v is held as it is, and the horizontal address h is reset to 0. jump address setup (1 dimensional addressing mode) write address setup write address setup write jump at least 64 clk cycles t wss t wsh t wah t was 01 2 a13 a12 a11 a1 a0 12 13 63 0 1 valid valid valid valid valid valid d(n) d(0) d(1) wck was wad wrs din note: the write jump address wa is (a , a , ... a ) add 'wa' 13 after 64 cycles have passed following the start of write address setup, a jump to the set address can be performed at any time. 12 0
datasheet title 28 read address setup rah t ras a13 a12 a11 a1 a0 read address setup read jump at least 64 clk cycles rck ras rad rrs dout note: 01 2 1213 630 1 t rss t t rsh valid valid valid valid valid the read jump address ra is (a , a , ... a ) d(n) d(0) d(1) add 'ra' after 64 cycles have passed following the start of read address setup, a jump to the set address can be performed at any time. read and write address setup can be performed asynchronously. 13 12 0 jump address setup (2 dimensional addressing mode 1) write address setup (2 dimensional addressing: 324 line 1024 dot mode) 0 1 8 9 10 13 63 01 wck was wad wrs din write address setup write jump at least 64 clk cycles note: add'w(v, h)' the write jump address w (v, h) is (v , ... , v , h , ... , h ) v8 v7 v0 h4 h3 h0 valid valid valid valid valid valid valid valid d(n) d(0) d(1) t t line address v t wsh wah t wss was the jump to the set address can be performed at any time once the required 64 cycles have passed following the start of write address setup. horizontal address h 8040
datasheet title 29 read address setup (2 dimensional addressing: 324 line 1024 dot mode) 0 1 8 9 10 13 63 01 rck ras rad rrs dout at least 64 clk cycles note: add 'r(v, h)' the read jump address r (v, h) is (v , ... , v , h , ... , h ) v8 v7 v0 h4 h3 h0 t t line address v horizontal address h t rsh rah t rss ras valid valid valid valid valid valid valid d(n) d(0) d(1) the jump to the set address can be performed at any time once the required 64 cycles have passed following the start of read address setup. read and write address setup can be performed asynchronously. 804 0 read address setup read jump jump address setup (2 dimensional addressing mode 2) write address setup (2 dimensional addressing: 288 line 1152 dot mode) 0 1 8 9 10 14 63 01 wck was wad wrs din at least 64 clk cycles note: add 'w(v, h)' the write jump address w (v, h) is (v , ... , v , h , ... , h ) v8 v7 v0 h5 h4 h0 valid valid valid valid valid valid valid valid d(n) d(0) d(1) t t line address v horizontal address h t wsh wah t wss was the jump to the set address can be performed at any time once the required 64 cycles have passed following the start of write address setup. 805 0 write address setup write jump
datasheet title 30 read address setup (2 dimensional addressing: 288 line 1152 dot mode) 0 1 8 9 10 14 63 01 rck ras rad rrs dont at least 64 clk cycles note: add'r(v, h)' the read jump address r (v, h) is (v , ... , v , h , ... , h ) v8 v7 v0 h5 h4 h0 t t line address v horizontal address h t rsh rah t rss ras valid valid valid valid valid valid valid d(n) d(0) d(1) the jump to the set address can be performed at any time once the required 64 cycles have passed following the start of read address setup. read and write address setup can be performed asynchronously. 8050 read address setup read jump address input mask t (t ) wck (rck) was (ras) wad (rad) wrs (rrs) note: in this example, only the line address is re-input, and the horizontal address retains its previously set value. v8 v7 v6 v0 01 2 8910 630 t (t ) wss rss t (t ) was ras wah rah t (t ) wsh rsh at least 64 clk cycles address setup jump after the start of read or write jump address setup, if ras or was respectively is returned to the high level at an arbitrary bit position, the address bits input thereafter are masked, and the corresponding bits retain their previous values.
datasheet title 31 jump write jump wck wrs was din note: n - 1 n 0 1 2 t wcc t wrh t wrs t wsh t wss t ds t dh t ds t dh d(n - 2) d(n - 1) d(n) d(0) d(1) d(2) add 'x' add 'wa' t wrs t wss wa is the address input in the previous write address setup cycle. read jump rck rrs ras dout note: n - 1 n 0 1 2 d(n - 1) d(n) d0 d1 d2 add 'x' add 'ra' t rrh t rrs t rsh t rss t rcc t rac t oh t rrs t rss ra is the address input in the previous read address setup cycle.
datasheet title 32 new/previous data access new data access (address reset) 0 1 2 3 160 161 162 wck we cgw wrs was din rck cgr rrs ras oe dout new 0 new 1 new 2 new 160 new 161 new 162 new 0 new 1 new 2 add '0' add '0' add '4' add '5' high high note: 01 2 written data can be read out 160 wck clock cycles after it was written.
datasheet title 33 previous data access (address reset) 0 1 2 3 32 33 34 wck we cgw wrs was din rck cgr rrs ras oe dout new 0 new 1 new 2 new 32 new 33 new 34 previous 0 previous 1 previous 2 add '0' add '0' add '1' high high note: 012 previous data can be read out up to 32 wck clock cycles after the write operation.
datasheet title 34 new data access (address jump) (example where the read and write jump addresses are to the same location) 0 1 2 13 160 161 162 wck we cgw wrs was din rck cgr rrs ras oe dout new 0 new 1 new 160 new 161 new 162 new 0 new 1 new 2 add 'a' add 'a' add 'a + 4' note: 01 2 add 'a + 5' written data can be read out 160 wck clock cycles after it was written. however, it is necessary to execute the read jump address setup operation outside the time period between 32 wck cycles before the start of write to that address and 32 wck cycles after the completion of write to that address.
datasheet title 35 previous data access (address jump) (example when the read and write jump addresses are to the same location) 01213 323334 wck we cgw wrs was din rck cgr rrs ras oe dout new 0 new 1 new 32 new 33 new 34 previous 0 previous 1 previous 2 add 'a' add 'a' add 'a + 1' note: 012 previous data can be read out up to 32 wck clock cycles after the write operation.
datasheet title 36 clear write clear wck wclr wwnd din wrs wlrs was n n + 1 0 1 2 t wcc t wclh t wcls t ds t dh d(n - 1) d(n) d(n + 1) d0 d1 d2 add(0, 0) add(v, h) note: the write address pointer is reset to (0, 0), and window mode is turned off if it was on. read clear t rcc n n + 1 0 1 2 t rcls t rclh t oh t rac d(n - 1) d(n) d(n + 1) d0 d1 d2 add(0, 0) add(v, h) rck rclr rwnd dout rrs rlrs ras note: the read address pointer is reset to (0, 0), and window mode is turned off if it was on.
datasheet title 37 window scan function combined window scan example in window scan mode, the destination address of a jump will be the first point in the window region, and line reset and reset operate as follows. line reset: resets to the left edge of the window on the next line. reset: resets to the first point in the window. in this mode, addresses are generated automatically internally, so this function is useful in applications that need to scan a window region. also, completely independent window regions can be scanned by the read and write systems. representative application examples are presented below. window a window b window c (m, n) (p, q) (r, s) (m + m, n + n) (p + p, q + q) (r + r, s + s) 0 0 319 1024(1152) h (32 bit units) v
datasheet title 38 case 1: switching between normal and window a scan wwnd (rwnd) mode wrs (rrs) was wlrs (ras) (rlrs) jump to (m, n) (m, n + 1) (m, n + n) jump to (0, 0) (1, 0) jump to (m, n) 1st line 2nd line last line in a 1st line 1st line 2nd line normal mode 2nd line last line window a window a case 2: repeatedly scanning window a wwnd (rwnd) mode wrs (rrs) was wlrs (ras) (rlrs) (m, n + 1) jump to (m, n) (m, n + 1) (m, n + n) 1st line 2nd line 1st line 2nd line window a last line in a window a jump to (m, n)
datasheet title 39 case 3: switching from window a scan to normal scan to window c scan (rwnd) mode wrs (rrs) was wlrs (ras) (rlrs) jump to (m, n) (m, n + n) jump to (0, (0, 1)0) 1 st line 2nd line last line in a window a window c normal 1st line 1st line 2nd line jump to (r, s) (r, s + 1) new address setup: (p, q) new address setup: (r, s) wwnd wclr (rclr) case 4: switching from window a scan to window b scan to window c scan (rwnd) mode wrs (rrs) was wlrs (ras) (rlrs) jump to (m, n) 1st line 2nd line last line in a window a jump to (r, s) (r, s + 1) new address setup: (p, q) new address setup: (r, s) wwnd (m, n + n) (p,q + 1) jump to (p, q) last line in b 1st line 1st line 2nd line window b widnow c (p,q+q)
datasheet title 40 window scan timing charts window jump (setup) n d(n - 1) note: the value (m, n) is the address input during the write address setup cycle. wck wrs was din wwnd n + 1 0 t wcc 12 t t wrs t wss wwds t wrh t wsh t wwdh t dh t ds t dh t ds d(n) d(n + 1) d0 d1 d2 add '(x, y)' add '(m, n)' ?write t wrs t wss wwds t window jump (setup) (cont) note: the value (m, n) is the address input during the read address setup cycle. rck dout rwnd n 0 t rcc rrs ras n + 1 12 t rrs t rss t rwds t rwdh t rsh t rrh t rac t oh add '(x, y)' add '(m, n)' d2 d1 d0 d(n + 1) d(n) ?read t rrs t rss rwds t
datasheet title 41 line increment (in window mode) note: the line address m is incremented and the horizontal address currently at n + n is reset to n. n - 1 wck wrs wwnd t wcc wlrs din wclr n t wlh t wls t ds t dh 01 2 high d(n - 1) d(n) d(0) d(1) d(2) don't care high add(m, n + n) add(m + 1, n) ?write t wls line increment (in window mode) (cont) n - 1 note: the line address m is incremented and the horizontal address currently at n + n is reset to n. wck rrs rwnd t rcc rlrs dout rclr n 0 12 t rlh t rls t rac t roh d(n) d(n - 1) d(1) d(2) d(0) add(m,n + n) add(m + 1,n) don't care high high ?read t rls
datasheet title 42 line hold (in window mode) note: the line address m is held at its current value and the horizontal address currently at n + n is reset to n. n - 1 wck wrs wwnd t wcc wlrs din wclr n t wlh 01 2 t wls t wrh t wrs t ds t dh d(n) d(n - 1) d(0) d(1) d(2) don't care high add(m, n + n) add(m, n) ?write t wls t wrs n - 1 note: the line address m is held at its current value and the horizontal address currently at n + n is reset to n. rck rrs rwnd t rcc rlrs dout rclr n0 1 2 t rlh t rls t rrs t rrh t rdh d(n - 1) d(n) d(0) d(1) d(2) t rac don't care high add(m, n + n) add(m, n) ?read t rls t rrs
datasheet title 43 window clear n wck was wwnd t wcc wrs din 0 n + 1 1 2 d(n - 1) d(n) d(n + 1) d 0 d1 d2 t wrh t wsh t wwdh t wrs t wss t wwds t ds t dh t ds t dh add'(x,y)' add'wa' note: 1. *1 ?write t wrs t wss the write address is reset to (0, 0) when was is high. when was is low, the write address jumps to wa, and in any case, the write window is cleared. n rck ras rwnd t rcc rrs dout n + 1 note: 1. 012 t rrh t rrh t rwdh t rac t rwds t oh t rss t rrs *1 d(n) d(n + 1) d0 d1 d2 add '(x, y)' add 'ra' ?read t rrs t rss the read address is reset to (0, 0) when ras is high. when ras is low, the read address jumps to ra, and in any case, the read window is cleared.
datasheet title 44 clear n wck wwnd din t wcc wclr n + 1 note: the write address pointer is reset to (0, 0), and window mode is turned off if it was on. wrs wlrs was 012 t wclh t wcls t ds t dh d(n - 1) d(n) d(n + 1) d 0 d 1 d 2 add(v, h) add(0, 0) ?write clear t wcls n rck rwnd dout t rcc rclr n + 1 note: the read address pointer is reset to (0, 0), and window mode is turned off if it was on. rrs rlrs ras d(n - 1) add(v, h) 012 t rclh t rcls t oh t rac add(0, 0) d(n) d(n + 1) d0 d1 d2 ?read clear t rcls
datasheet title 45 reset to the window origin these figures show the timing charts for resetting the address pointer to the window origin address (m, n) during window scan mode execution n wck was wwnd t wcc wrs din n + 1 note: the write address pointer is reset to the window origin address (m, n). 012 high t wrh t wwdh t wrs t wwds t ds t dh t ds t dh d(n - 1) d(n) d(n + 1) d 0 d 1 d 2 add '(m + m, n + n)' add '(m, n)' ?write t wrs t wwds n rck ras rwnd t rcc rrs dout n + 1 note: the read address pointer is reset to the window origin address (m, n). add '(m + m, n + n)' 012 t rrh t rwdh t rrs t rwds t rac t oh high d(n) d(n + 1) d0 d1 d2 add '(m, n)' ?read t rwds t rrs
datasheet title 46 package dimensions hm530281rtt series (ttp-44db) unit: mm 0.21 m 0.80 44 23 122 18.41 18.81 max 0.30 ?0.10 1.20 max 10.16 0.17 ?0.05 11.76 ?0.20 0 ?5 1.005 max 0.50 ?0.10 0.80 0.10 0.13 ?0.05
datasheet title 47 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071

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